Large area electronic devices, such as flat panel displays, sensor arrays, and space antennas, typically include large area sensor or light-emitting electronic cells that are addressed and/or controlled by thin film transistors (TFTs) and other electrical and electronic devices (e.g., passives and photodiodes). Such large area electronic devices are expensive to make by conventional photolithography techniques due to the relatively large size of the electronic cell arrays (e.g., 1000 cm2 or larger), and the relatively large spacing between adjacent TFTs. Conventional photolithography equipment for fabricating typical (i.e., ˜300 cm2 or smaller) IC devices is typically constructed to receive and process a semiconductor wafer having a predetermined size, and such wafers are typically much smaller than the substrate of a large area electronic device. Therefore, specialized equipment for photolithography on large area substrates must be developed typically at great expense. Moreover, conventional photolithography equipment includes optical and other processing tools that are constructed to facilitate the formation of substantially smaller feature sizes than those required in many elements of large area electronic devices, thereby making the production of large area electronic devices using such photolithography equipment highly inefficient.
Jet-printing is an emerging technology that attempts to reduce the costs associated with IC production by replacing expensive photolithographic processing with simple printing operations in which layer structures are formed using materials ejected from a print head. By printing an IC pattern directly on a device substrate rather than using the delicate and time-consuming lithography processes used in conventional IC manufacturing, an IC printing system can significantly reduce IC production costs. The printed IC pattern can either comprise actual IC features (i.e., elements that will be incorporated into the final IC, such as the gates and source and drain regions of TFTs, signal lines, the semiconductor, opto-electronic components, etc.), or it can be a mask printed onto the substrate that is used for subsequent semiconductor processing steps (e.g., etch, implant, etc.). Such masks are referred to herein as “jet-printed etch masks”.
Typically, jet-printing involves depositing a print solution (generally a material in a solvent or a liquid) by raster bitmap along a single axis (the “print travel axis”) across a solid substrate. Print heads, and in particular, the arrangements of the ejectors incorporated in those print heads, are optimized for printing along this print travel axis. The solid substrate is mounted under the print heads, and either the substrate is moved relative to the fixed print head, or the print head is moved over the fixed substrate. In either case, printing of an IC pattern takes place in a raster fashion, with the print head making “printing passes” across the substrate as the ejector(s) in the print head dispense individual droplets of print solution onto the substrate. At the end of each printing pass, the print head makes a perpendicular shift relative to the print travel axis before beginning a new printing pass. The print head continues making printing passes across the substrate in this manner until the IC pattern has been fully printed. Once dispensed from the ejector(s) of the print head, print solution droplets attach themselves to the substrate through a wetting action and proceed to either dry by evaporation of a carrier solvent or solidify in place if a pure material is deposited.
Because jet-printing of etch masks where the pattern is stored on a computer, which is also referred to as “digital lithography”, is not limited to a particular wafer size, it provides a promising technique for fabricating large area arrays of thin film transistors which are utilized, for example to drive large area displays or sensor arrays. However, at present, jet-printing is limited to producing relatively low resolution features (e.g., 30–50 microns), and therefore cannot meet all of the requirements for large area arrays. That is, much of the large area electronic device can be printed at low resolution (e.g., features) because wide metal lines are needed for interconnects. However, as discussed below, the transistors perform much better if they have very small features (e.g., approximately one micron), and are thus better suited to a high resolution printing process.
A problem with the large feature sizes produced by jet-printing techniques is that it places limitations on the speed and parasitic capacitance of TFTs forming the large area electronic device, and in many cases the high capacitance is the more serious problem. A generic design of the metal contacts to a TFT 1300 is shown in FIG. 13. TFT 1300 includes a gate region 1310, a source region 1320 and a drain region 1330, all formed from a conductive material, with source region 1320 and drain 1330 being separated from gate region 1310 by a dielectric layer (not shown). The conductance of TFT 1300 is proportional to W/L ratio formed by the source and drain structures of TFT 1300, where W is the width and L is the length of these structures. The area of TFT 1300 is W×L (width times length), the transit time is proportional to L2/mobility, and the parasitic capacitance is proportional to W×D, where D is the overlap distance of the gate and source regions and may be smaller than the feature size, but is of the same order of magnitude.
The operating speed of TFT 1300 is generally limited by RC time-constants, and ultimately by the RC time-constant of the TFT itself. A low resistance (high current) TFT requires a large W/L, but when fabricated with large feature sizes (e.g., a large D), this produces a high parasitic capacitance, which increases power consumption and reduces operating speed. In a simple approximation, the capacitance is proportional to the square of the feature size. As such, producing a large area electronic device using a relatively low resolution processing tool, such as jet-printing, results in relatively slow and inefficient TFTs. In particular, the jet-printing approach typically gives large feature sizes, and presently the size is 20–40 micron for conventional print-heads. The feature size can probably be reduced significantly, but it is doubtful whether it is possible to reach 1–2 micron, thus limiting the ability of jet-printing to produce low capacitance, high speed TFTs. However, jet-printing provides very good registration between different layers, because the accuracy of drop placement is limited only by the random variation in the drop ejection direction, and this can be reduced below 5 microns.
Soft lithography (a.k.a., stamping or microcontact printing) and imprint lithography are relatively high resolution printing techniques that facilitate the production of circuit structures having smaller features sizes (e.g., dimensions well below one micron have been demonstrated), and thus the production of much higher performance TFTs than those produced using jet-printing techniques. Soft lithography involves forming a printing press-like structure from a soft material (e.g., polydimethylsiloxane), which is referred to as a stamp, that prints a resist pattern directly onto a material (e.g., metal) layer deposited over a device substrate. The stamp is positioned (registered) over the desired substrate region using an appropriate X-Y positioning table, and then pressed against the device substrate with a predetermined force, thereby transferring a patterned resist layer onto the substrate. In another variation, a resist layer can be coated onto the substrate and embossed using the stamp in a process referred to as imprint lithography.
A problem with soft lithography is that the registration accuracy of different layers is relatively lower than that provided by jet-printing, and so the benefit of the small feature sizes is not realized in the production of large area electronic devices. Further, the production of large stamps (i.e., suitable for printing an entire critical layer of a large area electronic device) is difficult because of the potential for mechanical distortions in the features of the stamp.
What is needed is a method for producing ICs, and in particular, large area electronic devices, that includes both the cost efficiency of low resolution processing, but also provides the performance advantages associated with high resolution features.